High-performance PQC hardware
Parallel and unified polynomial cores that run every multiplication ML-KEM and ML-DSA need. ParallelNTT cuts NTT latency 24× on UltraScale+ FPGAs.
Bardia Taghavi
PhD Candidate, Florida Atlantic University · Cryptographic Hardware Engineer, PQSecure
Boca Raton, Florida · Born July 23, 1994
I design hardware for post-quantum cryptography. My work covers the polynomial arithmetic behind ML-KEM and ML-DSA, from tiny cores for IoT devices to fully parallel FPGA accelerators. I'm now extending this work to FALCON (FN-DSA).
News
- Three-hour tutorial on post-quantum cryptography for embedded systems at Embedded World North America 2026.
- Joined PQSecure Technologies as a Cryptographic Hardware Engineer.
- Book chapter High-Performance Post-Quantum Cryptographic Engineering in Hardware published by Springer.
- Gave the FAU Crypto Cafe talk on high-performance NTT design for ML-KEM and ML-DSA.
- Presented KNightCore at QRSEC (ACM CCS workshop), Taipei.
- Presented LightNTT at LightSEC 2025.
Research
Lightweight cryptography
Cores for constrained devices. KNightCore multiplies ML-KEM polynomials with zero DSP blocks; LightNTT uses a constant-geometry pipeline.
FALCON (FN-DSA)
New work on hardware for FALCON, the NTRU-lattice signature scheme NIST is standardizing as FN-DSA, with its floating-point FFT and Gaussian sampling.
Side-channel security
Masking and shuffling for polynomial arithmetic, and power-analysis attacks on hardware ML-DSA in a post-quantum root of trust.
Publications
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Springer 2026
High-Performance Post-Quantum Cryptographic Engineering in Hardware
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IEEE TCAD · Under review
HyperPoly: A High-Throughput Unified Core for Full-Spectrum Polynomial Arithmetic of ML-KEM and ML-DSA
- LightSEC 2025
- QRSEC @ CCS 2025
- GLSVLSI 2025
Talks & posters
Engineering post-quantum cryptography for embedded and resource-constrained systems
Two Birds, One Stone: high-performance NTT design for ML-KEM and ML-DSA
KNightCore: ultra-lightweight polynomial multiplier for ML-KEM
LightNTT: a tiny NTT/iNTT core for ML-DSA
From ultra-high-performance to ultra-lightweight NTT accelerators
ParallelNTT: maximizing NTT performance on FPGA
Crypto Cafe slides: PDF. The ewNA tutorial comes with a Jupyter notebook that implements ML-KEM and ML-DSA in pure Python (download .ipynb).
Teaching
A three-part lecture series on post-quantum cryptography, from first principles to the internals of ML-KEM and ML-DSA.
Introduction to post-quantum cryptography
Basics of KEMs and digital signatures
ML-KEM and ML-DSA, advanced
TA and lab instructor at FAU for Advanced FPGA Design, Cryptographic Engineering, Structured VLSI Design and Design of Digital Systems.
Experience
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Cryptographic Hardware Engineer
PQSecure Technologies · Boca Raton, FL
Post-quantum cryptography IP cores: arithmetic units for ML-KEM and ML-DSA across several architectures, from compact to high-throughput.
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Graduate Research Assistant
Florida Atlantic University · Cryptography & hardware design
PQC accelerators for ML-KEM and ML-DSA on Xilinx FPGAs, under Dr. Reza Azarderakhsh and Dr. Mehran Mozaffari Kermani.
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Mechatronics Engineer
Advanced Service Robots Lab, University of Tehran
Deep-learning gait analysis for amputee subjects on Raspberry Pi, with an STM32-based data acquisition system.
Education
PhD, Computer Engineering
Florida Atlantic University
MS, Mechatronics & Electronics
University of Tehran
BS, Electrical & Electronics Engineering
K. N. Toosi University of Technology
Service
Reviewer for IEEE HOST 2025 and 2026, ARITH 2026, IEEE Transactions on Computer-Aided Design (TCAD) and IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES).
Contact
For research collaboration, talks or PQC hardware questions: bardia.taghavi@pqsecurity.com or staghavi2024@fau.edu.